Low Power D Flip Flop Design for VLSI Applications
Keywords:
Flip-Flop (FF), DTCMOS, LECTOR, GALEOR, ONOFIC.Abstract
A flip-flop is a basic storage element used to store information. It is used to build RAM, latches, shift registers, counters, and other digital circuits. This paper proposes a new innovative design for D flip-flops. This design consumes much less power than previous flip-flop designs. The first proposed design introduces two gate-leakage transistors at the output gate using the GALEOR method. The second proposed design uses ONOFIC technology. Therefore, compared to the previous design, the power consumption of Design-I and Design-II is reduced by 35.61% and 34.36%, respectively. The proposed design is simulated using a Cadence tool using 90nm CMOS technology operating at 500MHz.
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