Design And Verification of Advanced Peripheral Bus Protocol Using Uvm

https://doi.org/10.55529/jaimlnn.12.1.9

Authors

  • Pavani Yammanuru M.Tech, VLSI,Sir C.V.Raman Institute of Technology and Scinces,Tadipatri,Anantapuramu
  • M.Amarnatha Reddy Assistant Professor & HOD , ECE, Sir C.V.Raman Institute of Technology and Scinces,Tadipatri, Anantapuramu

Keywords:

APB, AMBA, UVM, HDL, UART

Abstract

The System on chip uses advanced micro controller bus architecture is on chip bus introduced by ARM. Advanced peripheral bus is the component of the AMBA bus architecture. APB is low bandwidth, low power and low performance it used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This introduces the AMBA APB bus using UVM architecture design. The design created using the Verilog and HDL and tested by Verilog test bench and design is verified using universal verification  methodology. In this, we have a master and a slave. The master sends the control signals as a packet to the slave and the slave addresses the packet if both are equal we are getting transaction of write and read data, Where the master send the address slave recognize and it sends the signal to the master as a read data.

Published

2021-10-15

How to Cite

Pavani Yammanuru, & M.Amarnatha Reddy. (2021). Design And Verification of Advanced Peripheral Bus Protocol Using Uvm. Journal of Artificial Intelligence,Machine Learning and Neural Network (JAIMLNN) ISSN: 2799-1172, 1(02), 1–9. https://doi.org/10.55529/jaimlnn.12.1.9